DE.1) In which of the following base systems is 123 not a valid
number?
(a) Base 10
(b) Base 16
(c) Base 8
(d) Base 3
Answer is (d)
Explanation
In base 3, only 0, 1 and 2 are valid digits.
DE.2) A new Binary Coded Pentary (BCP) number system is proposed in
which every digit of a base-5 number is represented by its corresponding 3-bit
binary code. For example, the base-5 number 24 will be represented by its BCP
code 010100. In this number system, the BCP code 10010010001001 corresponds to
the following number in base-5 system
(a) 22211
(b) 11122
(c) 12244
(d) 44421
Answer is (a)
Explanation
Group the bits considering three each from right-most bit i.e.
10 ---- 010 ---- 010 ---- 001 ---- 001
Now decode them 2 2 2 1 1
DE.3) The output frequency of a frequency division circuit that
contains 12 flip-flops with an input clock frequency of 20.48 MHz is
(a) 10.24 kHz
(b) 5 kHz
(c) 30.24 kHz
(d) 15 kHz
Answer is (b)
Explanation
Output frequency = $\frac{input frequency}{(2^{n})}$ where n is the number of flip flops.
Thus fout$f_{out} = \frac{20.48MHz}{2^{12}}$
= 20.48MHz/4096
= 5 KHz
DE.4) The number of Boolean
functions that can be generated by n variables is equal to:
(a)$2^{n}$
(b)$2^{2^{n}}$
(c)$2^{n-1}$
(d)none of above
Answer is (b)
DE.5) Which statement BEST describes the operation of a negative-edge-triggered
D flip-flop?
(a) The logic level at the D input is transferred to Q on
negative edge of CLK
(b) The Q output is ALWAYS identical to the CLK input if the
D input is HIGH
(c) The Q output is ALWAYS identical to the D input when CLK
is positive
(d) The Q output is ALWAYS identical to the D input
Answer is (a)
DE.6)The minimum number of
2-input NAND gates required to implement the Boolean function Z = $A\overline{B}C$, assuming that A,B & C are available
(a)2
(b)3
(c)5
(d)6
Answer is (c)
DE.7)A simple flip-flop is
DE.9)The logic function;f =$\overline{[(x.\overline{y})+(\overline{x}.y)]}$is equivalent to
DE.12)Which of the following gate is a two-level logic gate?
(a)OR gate
(b)NAND gate
(c)EXCLUSIVE-OR gate
(d)NOT gate
Answer is (c)
DE.13)As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be
(a)very long
(b)very short
(c)at a maximum value to enable the input control signals to stabilize
(d)of no consequence as long as the levels are within the determinate range of value
Answer is (b)
DE.14)Assertion(A):A decoder is not a combinational circuit
Reason(R):Every memory element of semiconductor form has a decoder
(a)Both A & R are true and R is correct explanation of A
(b)Both A & R are true and R is NOT the correct explanation of A
(c)A is true but R is false
(d)A is false but R is true
Answer is (d)
DE.7)A simple flip-flop is
(a)a 2-bit memory
(b)a 1-bit memory
(c)a four state device
(d)has nothing to do with memory
Answer is (b)
DE.8)The expression A+$\overline{A}B$is equivalent to
DE.8)The expression A+$\overline{A}B$is equivalent to
(a)A+B
(b)AB+A
(c)AB
(d)AB+B
Answer is (a)
Answer is (a)
DE.9)The logic function;f =$\overline{[(x.\overline{y})+(\overline{x}.y)]}$is equivalent to
(a)$f=(x+y)(\overline{x}+\overline{y})$
(b)$f=\overline{[(\overline{x}+\overline{y})+(x+y)]}$
(c)xy
(d)none of above
Answer is (d) x xnor y
DE.10)A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the
(a)clock is LOW
(b)slave is transferring
(c)flip-flop is reset
(d)clock is HIGH
Answer is (d)
DE.11)A J-K flip-flop with J =1 and K =1 has 20kHz clock input.
The Q output is _____
(a)constantly LOW
(b)constantly HIGH
(c)a 20kHz square wave
(d)a 10kHz square wave
Answer is (d)
- Flip-flops change their state only when triggered(either by positive edge/negative edge)
- Assume positive edge triggered J-K flip-flop
Clk(in)= 20kHz=> 1/20kHz = 0.05ms
Therefore, output frequency = 1/0.1ms = 10kHz
Therefore, output frequency = 1/0.1ms = 10kHz
DE.12)Which of the following gate is a two-level logic gate?
(a)OR gate
(b)NAND gate
(c)EXCLUSIVE-OR gate
(d)NOT gate
Answer is (c)
DE.13)As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be
(a)very long
(b)very short
(c)at a maximum value to enable the input control signals to stabilize
(d)of no consequence as long as the levels are within the determinate range of value
Answer is (b)
DE.14)Assertion(A):A decoder is not a combinational circuit
Reason(R):Every memory element of semiconductor form has a decoder
(a)Both A & R are true and R is correct explanation of A
(b)Both A & R are true and R is NOT the correct explanation of A
(c)A is true but R is false
(d)A is false but R is true
Answer is (d)
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