DE.15) Chose the correct one from among the alternatives A,B,C,D after matching an item from Group 1 with the most appropriate item in Group 2:
Group 1: Group 2:
P. Shift register 1. Frequency division
Q. Counter 2. Addressing in memory chips
R. Decoder 3. Serial to parallel data conversion
(a) P-3, Q-2, R-1
(b) P-3, Q-1, R-2
(c) P-2, Q-1, R-3
(d) P-1, Q-2, R-3
Answer is ()
DE.16)A four bit shift register constructed using D-Latch has an initial state [0000].It is input with binary 1 .What is the output after 4 shifts?
(a)0100
(b)1000
(c)1111
(d)0000
Answer is ()
DE. 17) Setup time specifies:
(a)the minimum time the control levels need to be maintained on the inputs prior to the triggering edge of the clock in order to be reliably clocked into the flip-flop
(b)the maximum time interval required for the control levels to remain on the inputs before the triggered edge of the clock in order for the data to be reliably clocked out of the flip-flop
(c)how long the operator has to get the flip-flop running before the maximum power level is exceeded
(d)how long it takes the output to change states after the clock has transitioned
Answer is ()
DE.18) What is the difference between setup time and hold time?
(a)Setup time occurs after the active clock edge, hold time occurs before the active clock edge
(b)Setup time occurs before the active clock edge, hold time occurs after the active clock edge
(c)Setup time and hold time both occur at the active clock edge
(d)None of these
Answer is ()
DE.19) For a binary half sub tractor having two inputs A and B, the correct set of logical expressions for the outputs D (= A minus B) and X (= borrow) are
(a)𝐷 = 𝐴𝐵 + 𝐴̅𝐵, 𝑋 = 𝐴̅𝐵
(b)𝐷 = 𝐴̅𝐵 + 𝐴𝐵̅ + 𝐴𝐵̅, 𝑋 = 𝐴𝐵̅
(c)𝐷 = 𝐴̅𝐵 + 𝐴𝐵̅,𝑋 = 𝐴̅𝐵
(d)𝐷 = 𝐴𝐵 + 𝐴̅𝐵̅,𝑋 = 𝐴𝐵̅
Answer is ()
DE.20) Define a race condition for a flip-flop
(a)The inputs to a trigger device are changing slightly before the active trigger edge
(b)The inputs to a trigger device are changing slightly after the active trigger edge
(c)The inputs to a trigger device are changing at the same time as the active trigger edge
(d)None of these
Answer is ()
DE.21) A 2 bit binary multiplier can be implemented using
(a)2 input ANDs only
(b)2 input X-ORs and 4-input AND gates only
(c)Two (2) input NORs and one XNOR gate
(d) XOR gates and shift registers
Answer is ()
DE.22) What are the minimum number of 2-to-1 multiplexers required to generate a 2- input AND gate and a 2-input Ex-OR gate?
(a)1 and 2
(b)1 and 3
(c)1 and 1
(d)2 and 2
Answer is ()
DE.23)Figure shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in figure, output Y is
(a)0
(b)1
(c)AB
(d)Not(AB)
Answer is ()
DE.24) What is the major advantage of the J-K flip-flop over the S-R flip-flop?
(a)J-K flip-flop is much faster
(b)J-K flip-flop does not have propagation delay problems
(c)J-K flip-flop has a toggle state
(d)J-K flip-flop has two outputs
Answer is ()
DE.25) The time required for a pulse to change from .1 to .9 of it's maximum value is called:
(a)Rise time
(b)propagation time
(c)decay time
(d)operating speed
Answer is (a)
DE.26) The time required for a basic entity in logic design such as the gate or an inverter to change it's state is called:
(a)Propagation time
(b)Rise time
(c)decay time
(d)operating speed
Answer is (a)
DE.27) In a digital counter feedback loop is introduced
(a)Reduce the number of input pulses to reset the counter
(b)Improve stability
(c))reduce distortion
(d)asynchronous input and output pulses
Answer is ()
DE.28) The number of 2 to 1 multiplexers required to realize a 4 to 1 multiplexer is
(a)1
(b)2
(c)3
(d)4
Answer is (c)
(a) P-3, Q-2, R-1
(b) P-3, Q-1, R-2
(c) P-2, Q-1, R-3
(d) P-1, Q-2, R-3
Answer is ()
DE.16)A four bit shift register constructed using D-Latch has an initial state [0000].It is input with binary 1 .What is the output after 4 shifts?
(a)0100
(b)1000
(c)1111
(d)0000
Answer is ()
DE. 17) Setup time specifies:
(a)the minimum time the control levels need to be maintained on the inputs prior to the triggering edge of the clock in order to be reliably clocked into the flip-flop
(b)the maximum time interval required for the control levels to remain on the inputs before the triggered edge of the clock in order for the data to be reliably clocked out of the flip-flop
(c)how long the operator has to get the flip-flop running before the maximum power level is exceeded
(d)how long it takes the output to change states after the clock has transitioned
Answer is ()
DE.18) What is the difference between setup time and hold time?
(a)Setup time occurs after the active clock edge, hold time occurs before the active clock edge
(b)Setup time occurs before the active clock edge, hold time occurs after the active clock edge
(c)Setup time and hold time both occur at the active clock edge
(d)None of these
Answer is ()
DE.19) For a binary half sub tractor having two inputs A and B, the correct set of logical expressions for the outputs D (= A minus B) and X (= borrow) are
(a)𝐷 = 𝐴𝐵 + 𝐴̅𝐵, 𝑋 = 𝐴̅𝐵
(b)𝐷 = 𝐴̅𝐵 + 𝐴𝐵̅ + 𝐴𝐵̅, 𝑋 = 𝐴𝐵̅
(c)𝐷 = 𝐴̅𝐵 + 𝐴𝐵̅,𝑋 = 𝐴̅𝐵
(d)𝐷 = 𝐴𝐵 + 𝐴̅𝐵̅,𝑋 = 𝐴𝐵̅
Answer is ()
DE.20) Define a race condition for a flip-flop
(a)The inputs to a trigger device are changing slightly before the active trigger edge
(b)The inputs to a trigger device are changing slightly after the active trigger edge
(c)The inputs to a trigger device are changing at the same time as the active trigger edge
(d)None of these
Answer is ()
DE.21) A 2 bit binary multiplier can be implemented using
(a)2 input ANDs only
(b)2 input X-ORs and 4-input AND gates only
(c)Two (2) input NORs and one XNOR gate
(d) XOR gates and shift registers
Answer is ()
DE.22) What are the minimum number of 2-to-1 multiplexers required to generate a 2- input AND gate and a 2-input Ex-OR gate?
(a)1 and 2
(b)1 and 3
(c)1 and 1
(d)2 and 2
Answer is ()
DE.23)Figure shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in figure, output Y is
(a)0
(b)1
(c)AB
(d)Not(AB)
Answer is ()
DE.24) What is the major advantage of the J-K flip-flop over the S-R flip-flop?
(a)J-K flip-flop is much faster
(b)J-K flip-flop does not have propagation delay problems
(c)J-K flip-flop has a toggle state
(d)J-K flip-flop has two outputs
Answer is ()
DE.25) The time required for a pulse to change from .1 to .9 of it's maximum value is called:
(a)Rise time
(b)propagation time
(c)decay time
(d)operating speed
Answer is (a)
DE.26) The time required for a basic entity in logic design such as the gate or an inverter to change it's state is called:
(a)Propagation time
(b)Rise time
(c)decay time
(d)operating speed
Answer is (a)
DE.27) In a digital counter feedback loop is introduced
(a)Reduce the number of input pulses to reset the counter
(b)Improve stability
(c))reduce distortion
(d)asynchronous input and output pulses
Answer is ()
DE.28) The number of 2 to 1 multiplexers required to realize a 4 to 1 multiplexer is
(a)1
(b)2
(c)3
(d)4
Answer is (c)
